`include "common_def.v"
`include "decode_def.v"
module CPU(
input					 					clock,
input					 					reset,
input					 					io_interrupt,

input         					io_master_awready,
output        					io_master_awvalid,
output [3:0]   					io_master_awid,
output [31:0]  					io_master_awaddr,
output [7:0]   					io_master_awlen,
output [2:0]   					io_master_awsize,
output [1:0]   					io_master_awburst,
input         					io_master_wready,
output        					io_master_wvalid,
output [63:0]  					io_master_wdata,
output [7:0]   					io_master_wstrb,
output        					io_master_wlast,
output        					io_master_bready,
input         					io_master_bvalid,
input [3:0]    					io_master_bid,
input [1:0]    					io_master_bresp,
input         					io_master_arready,
output        					io_master_arvalid,
output [3:0]   					io_master_arid,
output [31:0]  					io_master_araddr,
output [7:0]   					io_master_arlen,
output [2:0]   					io_master_arsize,
output [1:0]   					io_master_arburst,
output        					io_master_rready,
input         					io_master_rvalid,
input [3:0]    					io_master_rid,
input [1:0]    					io_master_rresp,
input [63:0]   					io_master_rdata,
input         					io_master_rlast,

output        					io_slave_awready,
input         					io_slave_awvalid,
input [3:0]    					io_slave_awid,
input [31:0]   					io_slave_awaddr,
input [7:0]    					io_slave_awlen,
input [2:0]    					io_slave_awsize,
input [1:0]    					io_slave_awburst,
output        					io_slave_wready,
input         					io_slave_wvalid,
input [63:0]   					io_slave_wdata,
input [7:0]    					io_slave_wstrb,
input         					io_slave_wlast,
input         					io_slave_bready,
output        					io_slave_bvalid,
output [3:0]   					io_slave_bid,
output [1:0]   					io_slave_bresp,
output        					io_slave_arready,
input         					io_slave_arvalid,
input [3:0]    					io_slave_arid,
input [31:0]   					io_slave_araddr,
input [7:0]    					io_slave_arlen,
input [2:0]    					io_slave_arsize,
input [1:0]    					io_slave_arburst,
input         					io_slave_rready,
output        					io_slave_rvalid,
output [3:0]   					io_slave_rid,
output [1:0]   					io_slave_rresp,
output [63:0]  					io_slave_rdata,
output        					io_slave_rlast,

output [5:0]   					io_sram0_addr,
output        					io_sram0_cen,
output        					io_sram0_wen,
output [127:0] 					io_sram0_wmask,
output [127:0] 					io_sram0_wdata,
input [127:0]  					io_sram0_rdata,
output [5:0]   					io_sram1_addr,
output        					io_sram1_cen,
output        					io_sram1_wen,
output [127:0] 					io_sram1_wmask,
output [127:0] 					io_sram1_wdata,
input [127:0]  					io_sram1_rdata,
output [5:0]   					io_sram2_addr,
output        					io_sram2_cen,
output        					io_sram2_wen,
output [127:0] 					io_sram2_wmask,
output [127:0] 					io_sram2_wdata,
input [127:0]  					io_sram2_rdata,
output [5:0]   					io_sram3_addr,
output        					io_sram3_cen,
output        					io_sram3_wen,
output [127:0] 					io_sram3_wmask,
output [127:0] 					io_sram3_wdata,
input [127:0]  					io_sram3_rdata,
output [5:0]   					io_sram4_addr,
output        					io_sram4_cen,
output        					io_sram4_wen,
output [127:0] 					io_sram4_wmask,
output [127:0] 					io_sram4_wdata,
input [127:0]  					io_sram4_rdata,
output [5:0]   					io_sram5_addr,
output        					io_sram5_cen,
output        					io_sram5_wen,
output [127:0] 					io_sram5_wmask,
output [127:0] 					io_sram5_wdata,
input [127:0]  					io_sram5_rdata,
output [5:0]   					io_sram6_addr,
output        					io_sram6_cen,
output        					io_sram6_wen,
output [127:0] 					io_sram6_wmask,
output [127:0] 					io_sram6_wdata,
input [127:0]  					io_sram6_rdata,
output [5:0]   					io_sram7_addr,
output        					io_sram7_cen,
output        					io_sram7_wen,
output [127:0] 					io_sram7_wmask,
output [127:0] 					io_sram7_wdata,
input [127:0]  					io_sram7_rdata
);
//-------------------------------REGS----------------------------------//
wire 	[`WIDTH-1:0]			data_src1_R_DEp;
wire 	[`WIDTH-1:0]			data_src2_R_DEp;
wire	[`WIDTH-1:0] 			pc_R_F_FDp;
wire	[`WIDTH-1:0]			data1_R_FWU;
wire	[`WIDTH-1:0]			data2_R_FWU;
wire  [`WIDTH-1:0]			data_csr_w_E_CSR;
wire  [`WIDTH-1:0]  		data_dst_w__R;
//-------------------------------CSRS----------------------------------//
wire  [`WIDTH-1:0]			data_csr_r_CSR_E;
wire										interrupt_CSR_C_DEp;
wire  [`WIDTH-1:0]			mtvec_r_CSR_R;
//-------------------------------IFU------------------------------------//
wire										if_end_F_FDp;
wire	[31:0]						inst_F_FDp;
wire	[`WIDTH-1:0]			pc_F_IC;
wire										addr_valid_F_IC;
//-------------------------------FDp------------------------------------//
wire										if_start_FDp_F;
wire							  		write_pr_en_FDp_DEp;
wire										npc_valid_FDp_R;
wire	 									id_start_FDp_D;
wire										pc_recover_FDp_C;
wire [31:0]							inst_FDp_D_DEp;
wire [`WIDTH-1:0]				pc_FDp_DEp;
//-------------------------------IDU------------------------------------//
wire  [11:0]						addr_csr_D_DEp;
wire	[`R_ADDR_W-1:0]		addr_src1_D_R_DEp;
wire	[`R_ADDR_W-1:0]		addr_src2_D_R_DEp;
wire 										id_ready_D_FDp;
wire										id_valid_D_DEp;
wire		[3:0]						inst_key_D_DEp;
wire	[`R_ADDR_W-1:0]		addr_dst_D_DEp;
wire										wen_D_DEp;
wire 										wen_csr_D_DEp;
wire										is_ecall_D_DEp;
wire										is_mret_D_DEp;
wire										is_load_D_DEp;
wire 	[`WIDTH-1:0]			imm_D_DEp;
wire	[`OP_NUM-1:0]			alu_key_D_DEp;
wire	[`A_NUM-1:0]			alu_A_key_D_DEp;
wire	[`B_NUM-1:0]			alu_B_key_D_DEp;
wire  [`SHAMT_NUM-1:0]	shamt_key_D_DEp;
wire 										alu_result_key_D_DEp;
wire	[`RESULT_NUM-1:0]	result_key_D_DEp;
wire	[`CSR_KEY_NUM-1:0]data_csr_key_D_DEp;
wire 	[`LOAD_NUM-1:0]		load_data_key_D_DEp;
wire 	[7:0]							store_mask_D_DEp;
wire										read_en_D_DEp;
wire										write_en_D_DEp;
wire										is_fencei_D_DEp_FDp;
wire	[1:0]							mul_sign_key_D_DEp;
wire	[2:0]							ls_size_D_DEp;
wire										csr_i_or_r_key_D_DEp;
//-------------------------------DEP------------------------------------//
wire										DEp_ready_DEp_D;
wire										write_pr_en_DEP_ELSp_FWU;
wire										wen_csr_DEp_CSR;
wire										exe_start_DEp_E;
wire										pc_recover_DEp_C;
wire	[31:0]						inst_DEp_BJ;
wire	[`WIDTH-1:0]			pc_DEp_E_ELSp_CSR;
wire	[`WIDTH-1:0]			data_src1_DEp_;
wire	[`WIDTH-1:0]			data_src2_DEp_;
wire	[`WIDTH-1:0]			imm_DEp_E;
wire	[`OP_NUM-1:0]			alu_key_DEp_E;
wire	[`A_NUM-1:0]			alu_A_key_DEp_E;
wire	[`B_NUM-1:0]			alu_B_key_DEp_E;
wire	[`SHAMT_NUM-1:0]	shamt_key_DEp_E;
wire										alu_result_key_DEp_E;
wire	[`RESULT_NUM-1:0]	result_key_DEp_E;
wire	[`CSR_KEY_NUM-1:0]data_csr_key_DEp_E;
wire	[`LOAD_NUM-1:0]		load_data_key_DEp_ELSp;
wire	[7:0]							store_mask_DEp_ELSp;
wire										read_en_DEp_ELSp;
wire										write_en_DEp_ELSp;
wire										wen_DEp_ELSp;
wire										is_ecall_DEp_CSR;
wire										is_mret_DEp_CSR;
wire										is_load_DEp_ELSp;
wire	[`R_ADDR_W-1:0]		addr_dst_DEp_ELSp_FWU;
wire	[11:0]						addr_csr_DEp_CSR;
wire	[3:0]							inst_key_DEp_FWU;
wire 	[`R_ADDR_W-1:0]		addr_src1_DEp_FWU;
wire	[`R_ADDR_W-1:0]		addr_src2_DEp_FWU;
wire										is_fencei_DEp_ELSp;
wire	[1:0]							mul_sign_key_DEp_E;
wire										write_pr_en_DEp_C;
wire 	[2:0]							ls_size_DEp_ELSp;
wire										csr_i_or_r_key_DEp_E;
//-------------------------------EXU------------------------------------//
wire 										exe_ready_E_DEp;
wire 										exe_end_E_ELSp;
wire  [`WIDTH-1:0] 			data_dst_E_ELSp;
wire	[`WIDTH-1:0]			npc_E_R;
wire [`WIDTH-1:0]				address_E_ELSp;
wire [`WIDTH-1:0] 			src1__E;
wire [`WIDTH-1:0]				src2__E;
//-------------------------------ELSp-----------------------------------//
wire 										ELSp_ready_ELSp_E;
wire										write_pr_en_ELSp_LSRp_FWU;
wire										ls_start_ELSp_LS;
wire	[`LOAD_NUM-1:0]		load_data_key_ELSp_LS;
wire	[7:0]							store_mask_ELSp_LS;
wire										read_en_ELSp_LS;
wire										write_en_ELSp_LS;
wire	[`WIDTH-1:0]			address_ELSp_LS;
wire	[`WIDTH-1:0]			store_data_ELSp_LS;
wire										wen_ELSp_LSRp;
wire										is_load_ELSp_LSRp;
wire	[`R_ADDR_W-1:0]		addr_dst_ELSp_LSRp;
wire	[`WIDTH-1:0]			data_dst_ELSp_LSRp_FWU;
wire	[`WIDTH-1:0]			pc_ELSp_LSRp;//delete
wire										is_nouse_inst_ELSp_LSRp;//delete
wire [`WIDTH-1:0] 			store_data__ELSp;
wire										is_fencei_ELSp_LS;
wire	[2:0]							ls_size_ELSp_LS;
//-------------------------------LSU-----------------------------------//
wire										lsu_ready_LS_ELSp;
wire 										ls_end_LS_LSRp;
wire  [`WIDTH-1:0]			load_data_LS_LSRp;
wire										fencei_end_LS_FDp_ELSp;
wire  [`WIDTH-1:0]			address_LS_DC_CL;
wire										addr_r_valid_LS_DC;
wire										addr_w_valid_LS_DC;
wire	[`WIDTH-1:0]			store_data_LS_DC_CL;
wire	[7:0]							store_mask_LS_DC_CL;
wire										is_fencei_LS_DC;
wire										is_clint_LS_CL;
wire										clint_r_en_LS_CL;
wire										clint_w_en_LS_CL;
wire	[2:0]							ls_size_LS_DC;
//---------------------------LSU_REGS out-------------------------------//
wire	[`R_ADDR_W-1:0]		addr_dst_LSRp_R;
wire										wen_LSRp_R;
wire	[`WIDTH-1:0]			pc_LSRp_;//delete
wire 										LSRp_ready_LSRp_LS;
wire										write_pr_en_LSRp_FWU;
wire										is_load_LSRp_;
wire	[`WIDTH-1:0]			data_dst_LSRp_R_FWU;
wire	[`WIDTH-1:0]			load_data_LSRp_R_FWU;
wire										is_nouse_inst_LSRp_DIFF;//delete
wire										is_clint_LSRp_DIFF;//delete
//-----------------------------BJ unit-----------------------------------//
wire [`WIDTH-1:0] 			src1__BJ;
wire [`WIDTH-1:0]				src2__BJ;
wire										pc_jump_BJ_C;
wire  [`PC_NUM-1:0] 		pc_key_BJ_E;
//-----------------------------forwarding unit---------------------------//
wire	 [`R_ADDR_W-1:0]	addr1_FWU_R;
wire	 [`R_ADDR_W-1:0]	addr2_FWU_R;
wire										add_nouse_inst_FWU_BJ;
wire										src1_key_FWU_;
wire										src2_key_FWU_;
wire	[`WIDTH-1:0]			src1_forward_FWU_;
wire	[`WIDTH-1:0]			src2_forward_FWU_;
//-------------------------------Icache-----------------------------------//
wire	[31:0]						inst_IC_F;
wire										inst_valid_IC_F;
//-------------------------------Dcache-----------------------------------//
wire	[`WIDTH-1:0]			load_data_DC_LS;
wire										read_end_DC_LS;
wire										write_end_DC_LS;
wire										fencei_end_DC_LS;
//-------------------------------CLINT-----------------------------------//
wire										clint_r_end_CL_LS;
wire										clint_w_end_CL_LS;
wire [`WIDTH-1:0]				clint_rdata_CL_LS;
wire										mtip_CL_CSR;
wire										msip_CL_CSR;
//-------------------------------AXI-lite---------------------------------//
wire [`AWIDTH-1:0]			araddr_IC_A;
wire										arvalid_IC_A;
wire										arready_IC_A;
wire [`WIDTH-1:0]				rdata_IC_A;
wire [1:0]							rresp_IC_A;
wire										rvalid_IC_A;
wire										rready_IC_A;
wire	[2:0]							arsize_IC_A;

wire	[`AWIDTH-1:0]			araddr_DC_A;
wire										arvalid_DC_A;
wire										arready_DC_A;
wire		[`WIDTH-1:0]		rdata_DC_A;
wire		[1:0]						rresp_DC_A;
wire										rvalid_DC_A;
wire										rready_DC_A;
wire	[`AWIDTH-1:0]			awaddr_DC_A;
wire										awvalid_DC_A;
wire										awready_DC_A;
wire	[`WIDTH-1:0]			wdata_DC_A;
wire	[7:0]							wstrb_DC_A;
wire										wvalid_DC_A;
wire										wready_DC_A;
wire		[1:0]						bresp_DC_A;
wire										bvalid_DC_A;
wire										bready_DC_A;
wire										wlast_DC_A;
wire 		[2:0]						arsize_DC_A;
wire 		[2:0]						awsize_DC_A;
//------------------------------AXI-lite-to-AXI---------------------------//
assign 	io_master_awid[3:0] = 4'b0;
assign 	io_master_awlen[7:0] = 8'h00;
//assign 	io_master_awsize[2:0] =3'b010; //8byte
assign 	io_master_awburst[1:0] =2'b01;
//assign 	io_master_wlast = 1'b0;
assign 	io_master_arid[3:0] = 4'b0;
assign 	io_master_arlen[7:0] =8'h00;
//assign 	io_master_arsize[2:0] =3'b010;
assign 	io_master_arburst[1:0] =2'b01;
//assign 	io_master_bid[3:0];input
//assign 	io_master_rid[3:0];input
//assign 	io_master_rlast;input              				
//------------------------------nosued-output-signal----------------------//
assign 	io_slave_awready = 0;
assign 	io_slave_wready = 0;
assign 	io_slave_bvalid = 0;
assign 	io_slave_bid = 0;
assign 	io_slave_bresp = 0;
assign 	io_slave_arready = 0;
assign 	io_slave_rvalid = 0;
assign 	io_slave_rid = 0;
assign 	io_slave_rresp = 0;
assign 	io_slave_rdata = 0;
assign 	io_slave_rlast = 0;
//---------------------jump_stop ,add nouse inst and intrupt CTR----------------------//
wire 										jump_stop_C_;
wire										wash_C_;
assign 	jump_stop_C_ = pc_jump_BJ_C&(npc_E_R[`WIDTH-1:0]!=pc_DEp_E_ELSp_CSR[`WIDTH-1:0]+4)|intr_stop_C;
wire 										if_ready;
wire										if_ended_r;
Reg #(1,0)  if_ended_reg (clock,reset,if_start_FDp_F ?1'b0: if_end_F_FDp,if_ended_r,if_end_F_FDp|if_start_FDp_F);
assign if_ready = (if_ended_r | if_end_F_FDp)&(~if_start_FDp_F);

assign 		wash_C_ = jump_stop_C_ &if_ready & id_ready_D_FDp &exe_ready_E_DEp;
wire										add_nouse_inst_ready;
wire 										add_nouse_inst_C_;
assign  add_nouse_inst_ready = add_nouse_inst_C_&if_ready&id_ready_D_FDp&exe_ready_E_DEp&lsu_ready_LS_ELSp;
wire										add_nouse_inst_r;
Reg #(1,0)  add_nouse_inst_reg(clock,reset,add_nouse_inst_ready? 1'b0:1'b1,add_nouse_inst_r,add_nouse_inst_FWU_BJ|add_nouse_inst_ready);
assign add_nouse_inst_C_ = (add_nouse_inst_FWU_BJ|add_nouse_inst_r);
//add_start_C is a start signal for EXU,
//add_start0_C is one cycle before the add_start_C,is sim as the  p regs' wen signal
wire		add_start_r;
wire		add_start_C;
wire		add_start0_C;
Reg #(1,0) add_start_reg(clock,reset,add_nouse_inst_ready,add_start_r,1);
assign add_start0_C = add_nouse_inst_ready & (~add_start_r);
Reg #(1,0) add_start_delay_reg(clock,reset,add_start0_C,add_start_C,1);

wire							  pc_recover_C_R;
assign pc_recover_C_R = pc_recover_DEp_C|pc_recover_FDp_C;
//interrupt
wire								intr_stop_C;
Reg #(1,0) intr_stop_reg(clock,reset,wash_C_?0:write_pr_en_DEp_C,intr_stop_C,(write_pr_en_DEp_C&interrupt_CSR_C_DEp)|wash_C_);
wire								mti_happen_C_CSR;
assign	mti_happen_C_CSR = intr_stop_C & wash_C_;

//--------------------------------Modules start----------------------------//
MODULE_LS_REGS ls_reg_r(
	.clk_i								(clock),
	.rst_i								(reset),
	.LSRp_ready_o					(LSRp_ready_LSRp_LS),
	.ls_valid_i						(ls_end_LS_LSRp),
	.last_write_pr_en_i		(write_pr_en_ELSp_LSRp_FWU),
	.write_pr_en_o				(write_pr_en_LSRp_FWU),
	.wash_i								(wash_C_),//delete

	.wenR_i								(wen_ELSp_LSRp),
	.is_load_i						(is_load_ELSp_LSRp),
	.addr_dst_i						(addr_dst_ELSp_LSRp[`R_ADDR_W-1:0]),
	.data_dst_i						(data_dst_ELSp_LSRp_FWU[`WIDTH-1:0]),
	.load_data_i					(load_data_LS_LSRp[`WIDTH-1:0]),
	.pc_i									(pc_ELSp_LSRp[`WIDTH-1:0]),//delete
	.is_nouse_inst_i			(is_nouse_inst_ELSp_LSRp),//delete
	.is_clint_i						(is_clint_LS_CL&(clint_r_en_LS_CL|clint_w_en_LS_CL)),//delete

	.wenR_o								(wen_LSRp_R),
	.is_load_o						(is_load_LSRp_),
	.addr_dst_o						(addr_dst_LSRp_R[`R_ADDR_W-1:0]),
	.data_dst_o						(data_dst_LSRp_R_FWU[`WIDTH-1:0]),
	.pc_o									(pc_LSRp_[`WIDTH-1:0]),//delete
	.is_nouse_inst_o			(is_nouse_inst_LSRp_DIFF),//delete
	.is_clint_o						(is_clint_LSRp_DIFF),//delete
	.load_data_o					(load_data_LSRp_R_FWU[`WIDTH-1:0])
);

assign data_dst_w__R[`WIDTH-1:0] = is_load_LSRp_ ? load_data_LSRp_R_FWU[`WIDTH-1:0]: data_dst_LSRp_R_FWU[`WIDTH-1:0];
MODULE_REGS regs(
	.clk_i								(clock),
  .rst_i								(reset),
  .data_dst_w_i					(data_dst_w__R),
	.npc_i								(mti_happen_C_CSR ? mtvec_r_CSR_R:npc_E_R[`WIDTH-1:0]),
	.pc_jump_i						(wash_C_),
  .addr_dst_w_i					(addr_dst_LSRp_R[`R_ADDR_W-1:0]),
  .wen_i								(wen_LSRp_R),
  .addr_src1_r_i				(addr_src1_D_R_DEp[`R_ADDR_W-1:0]),
  .addr_src2_r_i				(addr_src2_D_R_DEp[`R_ADDR_W-1:0]),
  .data_src1_r_o				(data_src1_R_DEp[`WIDTH-1:0]),
  .data_src2_r_o				(data_src2_R_DEp[`WIDTH-1:0]),
  .pc_o									(pc_R_F_FDp[`WIDTH-1:0]),
	.npc_valid_i					(npc_valid_FDp_R),
	.pc_recover_i					(pc_recover_C_R),
	.pc_difftest_i				(pc_difftest[`WIDTH-1:0]), //delete
	.addr1_fw_i						(addr1_FWU_R[`R_ADDR_W-1:0]),
	.data1_fw_o						(data1_R_FWU[`WIDTH-1:0]),
	.addr2_fw_i						(addr2_FWU_R[`R_ADDR_W-1:0]),
	.data2_fw_o						(data2_R_FWU[`WIDTH-1:0])
);
MODULE_CSRS csrs(
.clk_i									(clock),
.rst_i									(reset),
.wen_csr_i							(wen_csr_DEp_CSR),
.addr_csr_r_i						(addr_csr_DEp_CSR[11:0]),
.addr_csr_w_i						(addr_csr_DEp_CSR[11:0]),
.data_csr_w_i						(data_csr_w_E_CSR[`WIDTH-1:0]),
.is_ecall_i							(is_ecall_DEp_CSR & wash_C_),
.is_mret_i							(is_mret_DEp_CSR & wash_C_),
.ecall_pc_i							(pc_DEp_E_ELSp_CSR[`WIDTH-1:0]),
.data_csr_r_o						(data_csr_r_CSR_E),
.mtvec_r_o							(mtvec_r_CSR_R),
.mtip_i									(mtip_CL_CSR),
.meip_i									(io_interrupt),
.msip_i									(msip_CL_CSR),
.interrupt_o						(interrupt_CSR_C_DEp),
.mintr_happen_i						(mti_happen_C_CSR)
);

MODULE_IFU ifu(
	.clk_i								(clock),
	.rst_i								(reset),
	.if_end_o							(if_end_F_FDp),
	.if_start_i						(if_start_FDp_F),
	.pc_i									(pc_R_F_FDp[`WIDTH-1:0]), 
	.inst_to_IDU_o				(inst_F_FDp[31:0]),

	.pc_o									(pc_F_IC[`WIDTH-1:0]),
	.addr_valid_o					(addr_valid_F_IC),
	.inst_i								(inst_IC_F[31:0]),
	.inst_valid_i					(inst_valid_IC_F)	
 );

MODULE_ICACHE icache(
	.clk_i								(clock),
	.rst_i								(reset),
	.pc_i									(pc_F_IC[`WIDTH-1:0]),
	.addr_valid_i					(addr_valid_F_IC),	
	.inst_o								(inst_IC_F[31:0]),
	.data_valid_o					(inst_valid_IC_F),

	.araddr_o							(araddr_IC_A),
	.arvalid_o						(arvalid_IC_A),
	.arready_i						(arready_IC_A),
	.rdata_i							(rdata_IC_A),
	.rresp_i							(rresp_IC_A),
	.rvalid_i							(rvalid_IC_A),
	.rready_o							(rready_IC_A),
	.arsize_o							(arsize_IC_A),
	
	.sram0_addr_o					(io_sram0_addr),
	.sram0_cen_o					(io_sram0_cen),
	.sram0_wen_o					(io_sram0_wen),
	.sram0_wmask_o				(io_sram0_wmask),
	.sram0_wdata_o				(io_sram0_wdata),
	.sram0_rdata_i				(io_sram0_rdata),
	.sram1_addr_o					(io_sram1_addr),
	.sram1_cen_o					(io_sram1_cen),
	.sram1_wen_o					(io_sram1_wen),
	.sram1_wmask_o				(io_sram1_wmask),
	.sram1_wdata_o				(io_sram1_wdata),
	.sram1_rdata_i				(io_sram1_rdata),
	.sram2_addr_o					(io_sram2_addr),
	.sram2_cen_o					(io_sram2_cen),
	.sram2_wen_o					(io_sram2_wen),
	.sram2_wmask_o				(io_sram2_wmask),
	.sram2_wdata_o				(io_sram2_wdata),
	.sram2_rdata_i				(io_sram2_rdata),
	.sram3_addr_o					(io_sram3_addr),
	.sram3_cen_o					(io_sram3_cen),
	.sram3_wen_o					(io_sram3_wen),
	.sram3_wmask_o				(io_sram3_wmask),
	.sram3_wdata_o				(io_sram3_wdata),
	.sram3_rdata_i				(io_sram3_rdata)
);

MODULE_IF_ID if_id_r(
	.clk_i								(clock),
	.rst_i								(reset),
	.if_valid_i						(if_end_F_FDp),
	.id_ready_i						(id_ready_D_FDp),
	.write_pr_en_o				(write_pr_en_FDp_DEp),
	.pc_change_start_o		(npc_valid_FDp_R),
	.id_start_o						(id_start_FDp_D),
	.if_start_o						(if_start_FDp_F),
	.stop_i								(jump_stop_C_),
	.wash_i								(wash_C_),
	.add_nouse_inst_i			(add_nouse_inst_C_),
	.add_start_i					(add_start_C),
	.pc_recover_o					(pc_recover_FDp_C),
	.is_fencei_i					(is_fencei_D_DEp_FDp),
	.fencei_end_add_start_i(fencei_end_LS_FDp_ELSp),

	.inst_i								(inst_F_FDp[31:0]),
	.pc_i									(pc_R_F_FDp[`WIDTH-1:0]),

	.inst_o								(inst_FDp_D_DEp[31:0]),
	.pc_o									(pc_FDp_DEp[`WIDTH-1:0])
);

MODULE_IDU idu(
	.id_start_i						(id_start_FDp_D),
	.id_ready_o						(id_ready_D_FDp),
	.id_valid_o						(id_valid_D_DEp),
	.DEp_ready_i					(DEp_ready_DEp_D),
	.inst_key_o						(inst_key_D_DEp[3:0]),
	.inst_i								(inst_FDp_D_DEp[31:0]),
	.addr_src1_o					(addr_src1_D_R_DEp[`R_ADDR_W-1:0]),
	.addr_src2_o					(addr_src2_D_R_DEp[`R_ADDR_W-1:0]),
	.addr_dst_o						(addr_dst_D_DEp[`R_ADDR_W-1:0]),
	.addr_csr_o						(addr_csr_D_DEp[11:0]),
	.wen_o								(wen_D_DEp),
	.wen_csr_o						(wen_csr_D_DEp),
	.is_ecall_o						(is_ecall_D_DEp),
	.is_mret_o						(is_mret_D_DEp),
	.is_fencei_o					(is_fencei_D_DEp_FDp),
	.is_load_o						(is_load_D_DEp),
	.imm_o								(imm_D_DEp[`WIDTH-1:0]),
	.alu_key_o						(alu_key_D_DEp[`OP_NUM-1:0]),
	.mul_sign_key_o				(mul_sign_key_D_DEp[1:0]),
	.alu_A_key_o					(alu_A_key_D_DEp[`A_NUM-1:0]),
	.alu_B_key_o					(alu_B_key_D_DEp[`B_NUM-1:0]),
	.shamt_key_o					(shamt_key_D_DEp[`SHAMT_NUM-1:0]),
	.alu_result_key_o			(alu_result_key_D_DEp),
	.result_key_o					(result_key_D_DEp[`RESULT_NUM-1:0]),
	.data_csr_key_o				(data_csr_key_D_DEp[`CSR_KEY_NUM-1:0]),
	.csr_i_or_r_key_o			(csr_i_or_r_key_D_DEp),
	.load_data_key_o			(load_data_key_D_DEp[`LOAD_NUM-1:0]),
	.ls_size_o						(ls_size_D_DEp[2:0]),
	.store_mask_o					(store_mask_D_DEp[7:0]),
	.read_en_o						(read_en_D_DEp),
	.write_en_o						(write_en_D_DEp)
);

MODULE_ID_EX	id_ex_r(
	.clk_i								(clock),
	.rst_i								(reset),
	.id_valid_i						(id_valid_D_DEp),
	.last_write_pr_en_i		(write_pr_en_FDp_DEp),
	.write_pr_en_o				(write_pr_en_DEP_ELSp_FWU),
	.DEp_ready_o					(DEp_ready_DEp_D),
	.exe_ready_i					(exe_ready_E_DEp),
	.exe_start_o					(exe_start_DEp_E),
	.stop_i								(jump_stop_C_),
	.intr_stop_i					(interrupt_CSR_C_DEp),
	.wash_i								(wash_C_),
	.add_nouse_inst_i			(add_nouse_inst_C_),
	.add_start_i					(add_start_C),
	.pc_recover_o					(pc_recover_DEp_C),
	.write_pr_en1_o				(write_pr_en_DEp_C),

	.inst_i								(inst_FDp_D_DEp[31:0]),
	.pc_i									(pc_FDp_DEp),
	.src1_i								(data_src1_R_DEp[`WIDTH-1:0]),
	.src2_i								(data_src2_R_DEp[`WIDTH-1:0]),
	.imm_i								(imm_D_DEp[`WIDTH-1:0]),
	.alu_key_i						(alu_key_D_DEp[`OP_NUM-1:0]),
	.mul_sign_key_i				(mul_sign_key_D_DEp[1:0]),
	.alu_A_key_i					(alu_A_key_D_DEp[`A_NUM-1:0]),
	.alu_B_key_i					(alu_B_key_D_DEp[`B_NUM-1:0]),
	.shamt_key_i					(shamt_key_D_DEp[`SHAMT_NUM-1:0]),
	.alu_result_key_i			(alu_result_key_D_DEp),
	.result_key_i					(result_key_D_DEp[`RESULT_NUM-1:0]),
	.data_csr_key_i				(data_csr_key_D_DEp[`CSR_KEY_NUM-1:0]),
	.csr_i_or_r_key_i			(csr_i_or_r_key_D_DEp),
	.load_data_key_i			(load_data_key_D_DEp[`LOAD_NUM-1:0]),
	.store_mask_i					(store_mask_D_DEp[7:0]),
	.read_en_i						(read_en_D_DEp),
	.write_en_i						(write_en_D_DEp),
	.wenR_i								(wen_D_DEp),
	.wen_csr_i						(wen_csr_D_DEp),
	.is_ecall_i						(is_ecall_D_DEp),
	.is_mret_i						(is_mret_D_DEp),
	.is_load_i						(is_load_D_DEp),
	.addr_dst_i						(addr_dst_D_DEp[`R_ADDR_W-1:0]),
	.addr_csr_i						(addr_csr_D_DEp[11:0]),
	.inst_key_i						(inst_key_D_DEp[3:0]),
  .addr_src1_r_i				(addr_src1_D_R_DEp[`R_ADDR_W-1:0]),
  .addr_src2_r_i				(addr_src2_D_R_DEp[`R_ADDR_W-1:0]),
	.is_fencei_i					(is_fencei_D_DEp_FDp),
	.ls_size_i						(ls_size_D_DEp[2:0]),
	
	.inst_o								(inst_DEp_BJ[31:0]),
	.pc_o									(pc_DEp_E_ELSp_CSR[`WIDTH-1:0]),
	.src1_o								(data_src1_DEp_[`WIDTH-1:0]),
	.src2_o								(data_src2_DEp_[`WIDTH-1:0]),
	.imm_o								(imm_DEp_E[`WIDTH-1:0]),
	.alu_key_o						(alu_key_DEp_E[`OP_NUM-1:0]),
	.mul_sign_key_o				(mul_sign_key_DEp_E[1:0]),
	.alu_A_key_o					(alu_A_key_DEp_E[`A_NUM-1:0]),
	.alu_B_key_o					(alu_B_key_DEp_E[`B_NUM-1:0]),
	.shamt_key_o					(shamt_key_DEp_E[`SHAMT_NUM-1:0]),
	.alu_result_key_o			(alu_result_key_DEp_E),
	.result_key_o					(result_key_DEp_E[`RESULT_NUM-1:0]),
	.data_csr_key_o				(data_csr_key_DEp_E[`CSR_KEY_NUM-1:0]),
	.csr_i_or_r_key_o			(csr_i_or_r_key_DEp_E),
	.load_data_key_o			(load_data_key_DEp_ELSp[`LOAD_NUM-1:0]),
	.store_mask_o					(store_mask_DEp_ELSp[7:0]),
	.read_en_o						(read_en_DEp_ELSp),
	.write_en_o						(write_en_DEp_ELSp),
	.wenR_o								(wen_DEp_ELSp),
	.wen_csr_o						(wen_csr_DEp_CSR),
	.is_ecall_o						(is_ecall_DEp_CSR),
	.is_mret_o						(is_mret_DEp_CSR),
	.is_load_o						(is_load_DEp_ELSp),
	.addr_dst_o						(addr_dst_DEp_ELSp_FWU[`R_ADDR_W-1:0]),
	.addr_csr_o						(addr_csr_DEp_CSR[11:0]),
	.inst_key_o						(inst_key_DEp_FWU[3:0]),
  .addr_src1_r_o				(addr_src1_DEp_FWU[`R_ADDR_W-1:0]),
  .addr_src2_r_o				(addr_src2_DEp_FWU[`R_ADDR_W-1:0]),
	.is_fencei_o					(is_fencei_DEp_ELSp),
	.ls_size_o						(ls_size_DEp_ELSp[2:0])
);


assign src1__BJ[`WIDTH-1:0] =src1_key_FWU_ ?src1_forward_FWU_[`WIDTH-1:0] :data_src1_DEp_[`WIDTH-1:0];
assign src2__BJ[`WIDTH-1:0] =src2_key_FWU_ ?src2_forward_FWU_[`WIDTH-1:0] :data_src2_DEp_[`WIDTH-1:0];
MODULE_B_Judge bjudge(
	.clk_i								(clock),
	.rst_i								(reset),
	.add_nouse_inst_i			(add_nouse_inst_FWU_BJ),
	.add_start_i					(add_start_C),
	.inst_i								(inst_DEp_BJ[31:0]),
	.src1_i								(src1__BJ[`WIDTH-1:0]),
	.src2_i								(src2__BJ[`WIDTH-1:0]),
	.pc_jump_o						(pc_jump_BJ_C),
	.pc_key_o							(pc_key_BJ_E[`PC_NUM-1:0])
);
assign src1__E[`WIDTH-1:0] =src1_key_FWU_ ? src1_forward_FWU_[`WIDTH-1:0] :data_src1_DEp_[`WIDTH-1:0];
assign src2__E[`WIDTH-1:0] =src2_key_FWU_ ?src2_forward_FWU_[`WIDTH-1:0] :data_src2_DEp_[`WIDTH-1:0];
MODULE_EXU exu(
	.clk_i								(clock),
	.rst_i								(reset),
	.ELSp_ready_i					(ELSp_ready_ELSp_E),
	.exe_ready_o					(exe_ready_E_DEp),
	.exe_end_o						(exe_end_E_ELSp),
	.exe_start_i					(exe_start_DEp_E),
	.src1_i								(src1__E[`WIDTH-1:0]),
	.src2_i								(src2__E[`WIDTH-1:0]),
	.csr_i								(data_csr_r_CSR_E[`WIDTH-1:0]),
	.pc_i									(pc_DEp_E_ELSp_CSR[`WIDTH-1:0]),
	.data_dst_o						(data_dst_E_ELSp[`WIDTH-1:0]),
	.data_csr_o						(data_csr_w_E_CSR[`WIDTH-1:0]),
	.npc_o								(npc_E_R[`WIDTH-1:0]),
	.imm_i								(imm_DEp_E),
	.alu_key_i						(alu_key_DEp_E[`OP_NUM-1:0]),
	.mul_sign_key_i				(mul_sign_key_DEp_E[1:0]),
	.alu_A_key_i					(alu_A_key_DEp_E[`A_NUM-1:0]),
	.alu_B_key_i					(alu_B_key_DEp_E[`B_NUM-1:0]),
	.shamt_key_i					(shamt_key_DEp_E[`SHAMT_NUM-1:0]),
	.pc_key_i							(pc_key_BJ_E[`PC_NUM-1:0]),
	.alu_result_key_i			(alu_result_key_DEp_E),
	.result_key_i					(result_key_DEp_E[`RESULT_NUM-1:0]),
	.data_csr_key_i				(data_csr_key_DEp_E[`CSR_KEY_NUM-1:0]),
	.csr_i_or_r_key_i			(csr_i_or_r_key_DEp_E),
	.address_o						(address_E_ELSp[`WIDTH-1:0])
);


assign store_data__ELSp[`WIDTH-1:0] = src2_key_FWU_? src2_forward_FWU_[`WIDTH-1:0] : data_src2_DEp_[`WIDTH-1:0];
MODULE_EX_LS ex_ls_r(
	.clk_i								(clock),
	.rst_i								(reset),
	.exe_valid_i					(exe_end_E_ELSp),
	.lsu_ready_i					(lsu_ready_LS_ELSp),
	.ELSp_ready_o					(ELSp_ready_ELSp_E),
	.last_write_pr_en_i		(write_pr_en_DEP_ELSp_FWU|add_start0_C),
	.write_pr_en_o				(write_pr_en_ELSp_LSRp_FWU),
	.ls_start_o						(ls_start_ELSp_LS),
	.wash_i								(wash_C_),//delete
	.fencei_end_i					(fencei_end_LS_FDp_ELSp),

	.load_data_key_i			(load_data_key_DEp_ELSp[`LOAD_NUM-1:0]),
	.store_mask_i					(store_mask_DEp_ELSp[7:0]),
	.read_en_i						(read_en_DEp_ELSp),
	.write_en_i						(write_en_DEp_ELSp),
	.address_i						(address_E_ELSp[`WIDTH-1:0]),
	.store_data_i					(store_data__ELSp),
	.wenR_i								(wen_DEp_ELSp),
	.is_load_i						(is_load_DEp_ELSp),
	.addr_dst_i						(addr_dst_DEp_ELSp_FWU[`R_ADDR_W-1:0]),
	.data_dst_i						(data_dst_E_ELSp[`WIDTH-1:0]),
	.pc_i									(pc_DEp_E_ELSp_CSR[`WIDTH-1:0]),//delete
	.add_nouse_inst_i			(add_nouse_inst_C_),//delete
	.is_fencei_i					(is_fencei_DEp_ELSp),
	.ls_size_i						(ls_size_DEp_ELSp[2:0]),

	.load_data_key_o			(load_data_key_ELSp_LS[`LOAD_NUM-1:0]),
	.store_mask_o					(store_mask_ELSp_LS[7:0]),
	.read_en_o						(read_en_ELSp_LS),
	.write_en_o						(write_en_ELSp_LS),
	.address_o						(address_ELSp_LS[`WIDTH-1:0]),
	.store_data_o					(store_data_ELSp_LS[`WIDTH-1:0]),
	.wenR_o								(wen_ELSp_LSRp),
	.is_load_o						(is_load_ELSp_LSRp),
	.addr_dst_o						(addr_dst_ELSp_LSRp[`R_ADDR_W-1:0]),
	.data_dst_o						(data_dst_ELSp_LSRp_FWU[`WIDTH-1:0]),
	.pc_o									(pc_ELSp_LSRp[`WIDTH-1:0]),//delete
	.is_nouse_inst_o			(is_nouse_inst_ELSp_LSRp),//delete
	.is_fencei_o					(is_fencei_ELSp_LS),
	.ls_size_o						(ls_size_ELSp_LS[2:0])
);

MODULE_LSU lsu(
.clk_i									(clock),
.rst_i									(reset),
.lsu_ready_o						(lsu_ready_LS_ELSp),
.ls_end_o								(ls_end_LS_LSRp),
.LSRp_ready_i						(LSRp_ready_LSRp_LS),
.is_fencei_i						(is_fencei_ELSp_LS),
.fencei_end_o						(fencei_end_LS_FDp_ELSp),

.store_data_i						(store_data_ELSp_LS[`WIDTH-1:0]),
.load_data_o						(load_data_LS_LSRp[`WIDTH-1:0]),
.read_en_i							(read_en_ELSp_LS),
.write_en_i							(write_en_ELSp_LS),
.store_mask_i						(store_mask_ELSp_LS[7:0]),
.load_data_key_i				(load_data_key_ELSp_LS[`LOAD_NUM-1:0]),
.ls_size_i							(ls_size_ELSp_LS[2:0]),
.address_i							(address_ELSp_LS[`WIDTH-1:0]),
.ls_start_i							(ls_start_ELSp_LS),

.address_o							(address_LS_DC_CL[`WIDTH-1:0]),
.addr_r_valid_o					(addr_r_valid_LS_DC),
.load_data_i						(load_data_DC_LS[`WIDTH-1:0]),
.read_end_i							(read_end_DC_LS|clint_r_end_CL_LS),
.addr_w_valid_o					(addr_w_valid_LS_DC),
.store_data_o						(store_data_LS_DC_CL[`WIDTH-1:0]),
.store_mask_o						(store_mask_LS_DC_CL[7:0]),
.write_end_i						(write_end_DC_LS|clint_w_end_CL_LS),
.is_fencei_o						(is_fencei_LS_DC),
.fencei_end_i						(fencei_end_DC_LS),
.ls_size_o							(ls_size_LS_DC[2:0]),
.is_clint_o							(is_clint_LS_CL),
.clint_data_i						(clint_rdata_CL_LS[`WIDTH-1:0]),
.clint_w_en_o						(clint_w_en_LS_CL),
.clint_r_en_o						(clint_r_en_LS_CL)
);
MODULE_CLINT clint(
.clk_i									(clock),
.rst_i									(reset),
.clint_addr_i						(address_LS_DC_CL[`WIDTH-1:0]),
.clint_ren_i						(clint_r_en_LS_CL),
.clint_rdata_o					(clint_rdata_CL_LS[`WIDTH-1:0]),
.clint_wen_i						(clint_w_en_LS_CL),
.clint_wdata_i					(store_data_LS_DC_CL[`WIDTH-1:0]),
.clint_wmask_i					(store_mask_LS_DC_CL[7:0]),
.is_clint_i							(is_clint_LS_CL),
.clint_rend_o						(clint_r_end_CL_LS),
.clint_wend_o						(clint_w_end_CL_LS),
.mtip_o									(mtip_CL_CSR),
.msip_o									(msip_CL_CSR)
);
MODULE_DCACHE dcache(
.clk_i									(clock),
.rst_i									(reset),
.addr_i									(address_LS_DC_CL[`WIDTH-1:0]),
.addr_r_valid_i					(addr_r_valid_LS_DC),	
.data_r_o								(load_data_DC_LS[`WIDTH-1:0]),
.read_end_o							(read_end_DC_LS),
.addr_w_valid_i					(addr_w_valid_LS_DC),
.data_w_i								(store_data_LS_DC_CL[`WIDTH-1:0]),
.w_mask_i								(store_mask_LS_DC_CL[7:0]),
.w_end_o								(write_end_DC_LS),
.is_fencei_i						(is_fencei_LS_DC),
.fencei_end_o						(fencei_end_DC_LS),
.ls_size_i							(ls_size_LS_DC[2:0]),

.araddr_o								(araddr_DC_A),
.arvalid_o							(arvalid_DC_A),
.arready_i							(arready_DC_A),
.rdata_i								(rdata_DC_A),
.rresp_i								(rresp_DC_A),
.rvalid_i								(rvalid_DC_A),
.rready_o								(rready_DC_A),
.awaddr_o								(awaddr_DC_A),
.awvalid_o							(awvalid_DC_A),
.awready_i							(awready_DC_A),
.wdata_o								(wdata_DC_A),
.wstrb_o								(wstrb_DC_A),
.wvalid_o								(wvalid_DC_A),
.wready_i								(wready_DC_A),
.bresp_i								(bresp_DC_A),
.bvalid_i								(bvalid_DC_A),
.bready_o								(bready_DC_A),
.wlast_o								(wlast_DC_A),
.arsize_o								(arsize_DC_A),
.awsize_o								(awsize_DC_A),

.sram4_addr_o						(io_sram4_addr),
.sram4_cen_o						(io_sram4_cen),
.sram4_wen_o						(io_sram4_wen),
.sram4_wmask_o					(io_sram4_wmask),
.sram4_wdata_o					(io_sram4_wdata),
.sram4_rdata_i					(io_sram4_rdata),
.sram5_addr_o						(io_sram5_addr),
.sram5_cen_o						(io_sram5_cen),
.sram5_wen_o						(io_sram5_wen),
.sram5_wmask_o					(io_sram5_wmask),
.sram5_wdata_o					(io_sram5_wdata),
.sram5_rdata_i					(io_sram5_rdata),
.sram6_addr_o						(io_sram6_addr),
.sram6_cen_o						(io_sram6_cen),
.sram6_wen_o						(io_sram6_wen),
.sram6_wmask_o					(io_sram6_wmask),
.sram6_wdata_o					(io_sram6_wdata),
.sram6_rdata_i					(io_sram6_rdata),
.sram7_addr_o						(io_sram7_addr),
.sram7_cen_o						(io_sram7_cen),
.sram7_wen_o						(io_sram7_wen),
.sram7_wmask_o					(io_sram7_wmask),
.sram7_wdata_o					(io_sram7_wdata),
.sram7_rdata_i					(io_sram7_rdata)
);
MODULE_AXI_Arbiter axi_arbiter(
.clk_i									(clock),
.rst_i									(reset),
.araddr_F_i							(araddr_IC_A),
.arvalid_F_i						(arvalid_IC_A),
.arready_F_o						(arready_IC_A),
.rdata_F_o							(rdata_IC_A),
.rresp_F_o							(rresp_IC_A),
.rvalid_F_o							(rvalid_IC_A),
.rready_F_i							(rready_IC_A),
.arsize_F_i							(arsize_IC_A),

.araddr_LS_i						(araddr_DC_A),
.arvalid_LS_i						(arvalid_DC_A),
.arready_LS_o						(arready_DC_A),
.rdata_LS_o							(rdata_DC_A),
.rresp_LS_o							(rresp_DC_A),
.rvalid_LS_o						(rvalid_DC_A),
.rready_LS_i						(rready_DC_A),
.awaddr_LS_i						(awaddr_DC_A),
.awvalid_LS_i						(awvalid_DC_A),
.awready_LS_o						(awready_DC_A),
.wdata_LS_i							(wdata_DC_A),
.wstrb_LS_i							(wstrb_DC_A),
.wvalid_LS_i						(wvalid_DC_A),
.wready_LS_o						(wready_DC_A),
.bresp_LS_o							(bresp_DC_A),
.bvalid_LS_o						(bvalid_DC_A),
.bready_LS_i						(bready_DC_A),
.wlast_LS_i							(wlast_DC_A),
.arsize_LS_i						(arsize_DC_A),
.awsize_LS_i						(awsize_DC_A),

.araddr_o								(io_master_araddr),
.arvalid_o							(io_master_arvalid),
.arready_i							(io_master_arready),
.rdata_i								(io_master_rdata),
.rresp_i								(io_master_rresp),
.rvalid_i								(io_master_rvalid),
.rready_o								(io_master_rready),
.awaddr_o								(io_master_awaddr),
.awvalid_o							(io_master_awvalid),
.awready_i							(io_master_awready),
.wdata_o								(io_master_wdata),
.wstrb_o								(io_master_wstrb),
.wvalid_o								(io_master_wvalid),
.wready_i								(io_master_wready),
.bresp_i								(io_master_bresp),
.bvalid_i								(io_master_bvalid),
.bready_o								(io_master_bready),
.wlast_o								(io_master_wlast),
.arsize_o								(io_master_arsize),
.awsize_o								(io_master_awsize)
);
MODULE_Forward_Unit forwarding_uint (
.clk_i									(clock),
.rst_i									(reset),
.add_start_i						(add_start0_C),
.IDR_wen_i							(write_pr_en_DEP_ELSp_FWU),
.EXR_wen_i							(write_pr_en_ELSp_LSRp_FWU),
.LSR_wen_i							(write_pr_en_LSRp_FWU),
.inst_key_IDR_i					(inst_key_DEp_FWU[3:0]),
.addr_src1_IDR_i				(addr_src1_DEp_FWU[`R_ADDR_W-1:0]),
.addr_src2_IDR_i				(addr_src2_DEp_FWU[`R_ADDR_W-1:0]),
.addr_dst_IDR_i					(addr_dst_DEp_ELSp_FWU[`R_ADDR_W-1:0]),

.data_dst_EXR_i					(data_dst_ELSp_LSRp_FWU[`WIDTH-1:0]),
.data_dst_LSR_i					(data_dst_LSRp_R_FWU[`WIDTH-1:0]),
.load_data_LSR_i				(load_data_LSRp_R_FWU[`WIDTH-1:0]),	

.add_nouse_inst_o				(add_nouse_inst_FWU_BJ),
.src1_key_o							(src1_key_FWU_),
.src2_key_o							(src2_key_FWU_),
.src1_forward_o					(src1_forward_FWU_),
.src2_forward_o					(src2_forward_FWU_),

.data1_regs_i						(data1_R_FWU[`WIDTH-1:0]),
.addr1_regs_o						(addr1_FWU_R[`R_ADDR_W-1:0]),
.data2_regs_i						(data2_R_FWU[`WIDTH-1:0]),
.addr2_regs_o						(addr2_FWU_R[`R_ADDR_W-1:0])
);


//-------------------------------difftest----------------------------------//
wire [`WIDTH-1:0] pc_difftest1;//delete
wire [`WIDTH-1:0] pc_difftest;//delete
assign pc_difftest1 = pc_LSRp_[`WIDTH-1:0];//delete
Reg #(`WIDTH,0) pc_difftest_reg(clock,reset,pc_difftest1,pc_difftest,1);//delete
wire is_nouse_inst;//delete
Reg #(1,0) is_nouse_inst_reg (clock,reset,is_nouse_inst_LSRp_DIFF,is_nouse_inst,1);//delete
//delete
//delete
export "DPI-C" function GET_NPC;//delete
function void GET_NPC();//delete
		output bit[`WIDTH-1:0] npc;//delete
		npc[`WIDTH-1:0] = npc_E_R[`WIDTH-1:0];//delete
endfunction//delete
//DPI-C write_back;//delete
wire	has_writing_back;//delete
wire is_writing_back;//delete
wire is_writing_back1;//delete
Reg #(1,0) is_write_back (clock,reset,write_pr_en_LSRp_FWU,is_writing_back1,1);//delete
Reg #(1,0) is_write_back1 (clock,reset,is_writing_back1,is_writing_back,1);//delete
assign has_writing_back = is_writing_back &(~is_nouse_inst);//delete
export "DPI-C" function WRITE_BACK;//delete
function void WRITE_BACK();//delete
				output bit is_writing_back;//delete
				is_writing_back=has_writing_back;//delete
endfunction//delete

wire is_intr_r;//delete
wire is_intr;//delete
Reg #(1,0) is_intr_delay_r(clock,reset,(pc_LSRp_==mtvec_r_CSR_R)?0:mti_happen_C_CSR,is_intr_r,mti_happen_C_CSR|(pc_LSRp_==mtvec_r_CSR_R));//delete
assign is_intr = is_intr_r &	(pc_LSRp_==mtvec_r_CSR_R);//delete
export "DPI-C" function IS_INTR;//delete
function void IS_INTR();//delete
				output bit is_intr;//delete
				is_intr=is_intr_r &	(pc_LSRp_==mtvec_r_CSR_R);//delete
endfunction//delete
wire is_ls_clint;//delete
wire is_ls_clint_r;//delete
Reg #(1,0) is_ls_clint_reg(clock,reset,is_clint_LSRp_DIFF,is_ls_clint_r,1);//delete
assign is_ls_clint = is_ls_clint_r&is_writing_back;//delete
export "DPI-C" function IS_CLINT;//delete
function void IS_CLINT();//delete
				output bit is_ls_clint;//delete
				is_ls_clint=is_ls_clint_r&is_writing_back;//delete
endfunction//delete
//-------------------------------debug----------------------------------//
MODULE_debug debug1(//delete
.aclk_i					(clock),//delete
.bpc_IFR				(pc_FDp_DEp[`WIDTH-1:0]),//delete
.cpc_IDR				(pc_DEp_E_ELSp_CSR[`WIDTH-1:0]),//delete
.dpc_EXR				(pc_ELSp_LSRp[`WIDTH-1:0]),//delete
.epc_LSR				(pc_LSRp_[`WIDTH-1:0]),//delete
.fpc_diff				(pc_difftest),//delete
.gdiff					(has_writing_back),//delete
.hif_start			(if_start_FDp_F),//delete
.if_end					(if_end_F_FDp),//delete
.jid_start			(id_start_FDp_D),//delete
.kid_end				(id_valid_D_DEp),//delete
.lex_start_i		(exe_start_DEp_E),//delete
.mex_end_i			(exe_end_E_ELSp),//delete
.nls_start_i		(ls_start_ELSp_LS),//delete
.ols_end_i			(ls_end_LS_LSRp)//delete
);//delete
endmodule
